Electronic design automation (EDA) – File Formats

  • BRD – Board file for EAGLE Layout Editor, a commercial PCB design tool
  • BSDL – Description language for testing through JTAG
  • CDL – Transistor-level netlist format for IC design
  • CPF – Power-domain specification in SoC implementation (see also UPF)
  • DEF – Gate-level layout
  • DSPF – Detailed Standard Parasitic Format, Analog-level parasitics of interconnections in IC design
  • EDIF – Vendor neutral gate-level netlist format
  • FSDB – Analog waveform format (see also Waveform viewer)
  • GDSII – Format for PCB and layout of integrated circuits
  • HEX – ASCII-coded binary format for memory dumps
  • LEF – Library Exchange Format, physical abstract of cells for IC design
  • LIB – Library modeling (function, timing) format
  • MS12 – NI Multisim file
  • OASIS – Open Artwork System Interchange Standard
  • OpenAccess – Design database format with APIs
  • SDC – Synopsys Design Constraints, format for synthesis constraints
  • SDF – Standard for gate-level timings
  • SPEF – Standard format for parasitics of interconnections in IC design
  • SPI, CIR – SPICE Netlist, device-level netlist and commands for simulation
  • SREC, S19 – S-record, ASCII-coded format for memory dumps
  • STIL – Standard Test Interface Language, IEEE1450-1999 standard for Test Patterns for IC
  • SV – SystemVerilog source file
  • UPF – Standard for Power-domain specification in SoC implementation
  • V – Verilog source file
  • VCD – Standard format for digital simulation waveform
  • VHD, VHDL – VHDL source file
  • WGL – Waveform Generation Language, format for Test Patterns for IC

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